1. Field of the Invention
This invention relates to the manufacture of semiconductor devices and, more particularly, to a method of manufacturing integration semiconductor devices with high integration density and high precision.
2. Description of the Prior Art
To manufacture a semiconductor device such as a bipolar type high frequency transistor device, it has been the practice, for instance, to form an n.sup.+ -type buried layer 2 in a p-type silicon substrate 1 and epitaxially grow an n-type silicon layer 3 on the entire surface of the substrate 1, as shown in FIG. 1. Then, the epitaxial layer 3 is isolated into island regions by silicon oxide layers 4 formed by selective etching, followed by masked oxidation. Subsequently, phosphorus is diffused into the smaller island region to form a collector contact region 5. Then, a base active layer 6a is formed through ion implantation of boron into the larger island region, and a base contact region 6b of high impurity concentration is formed through diffusion of boron. Thereafter, a silicon oxide film 7 is formed, and contact holes 8 and 9 are formed for an emitter region and the collector contact region. The emitter region 11 is then formed by covering the emitter contact hole 8 with a patterned polycrystalline layer (hereinafter referred to as polysilicon layer) 10 doped with an impurity such as arsenic or phosphorus and diffusing the impurity into the epitaxial layer. A base contact hole 12 is formed, and, finally, electrodes 13 are formed to be electrically connected to each region through each contact hole.
In this prior art method, the emitter region 11 is formed after the formation of the base contact region 6b. In this case, the sole positioning of these regions requires two distinct steps and thus necessitates an allowance which is double the positioning allowance in each step. This is undesired from the standpoint of the higher density of integration.
Japanese Patent Disclosure No. 53-91672 discloses a method, in which the base contact region 6b is formed by ion implantation using, as a mask, the patterned polysilicon layer 10 which covers the emitter region contact hole 8 and extends over the silicon oxide film. However, again in this method the polysilicon film 10 which serves as a mask at the time of the ion implantation is patterned after the positioning of the emitter region (i.e., the positioning of the emitter region contact hole 8). Therefore, a similar allowance to that in the aforementioned prior art is necessary.
Japanese Patent Disclosure 54-20675 discloses a method, which makes use of a patterned laminated layer, which is formed over the eventual emitter region and consists of a silicon oxide film and a silicon nitride film formed thereon. This laminated layer is used as a mask for the ion implantation to form the base active layer 6a and base contact region 6b. The silicon layer is then thermally oxidized to form a silicon oxide layer. Then, the emitter region 11 is formed by removing the laminated film and doping an impurity from the exposed surface. With this method, the silicon layer immediately beneath the laminated layer is laterally oxidized in the thermal oxidation step, and the emitter region can thus be spaced apart from the base contact region to the extent corresponding to the oxidized portion of the silicon layer. However, the growth of the thermal oxide film, which is comparatively thick, strains the silicon layer and deteriorates the emitter junction characteristics. In addition, a positioning error of the base contact hole, which is formed afterwards, is inevitable.